1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatus for defect isolation within integrated circuits.
2. Background
A circuit design may include a plurality of latches, such as shift register latches (SRLs), catenated to form a level sensitive scan design (LSSD) scan chain. If a circuit design is determined to be defective, existing test methods (e.g., scan based design methodologies) may be used for testing and diagnosing the circuit design. More specifically, the scan based design test methodologies may be used to identify a faulty latch (e.g., SRL) included in a LSSD scan chain. However, when the LSSD scan chain is defective and access to the internal logic of the circuit design is greatly reduced, rapid and accurate diagnosis of the fault or defect using such test methodologies is inhibited.
Existing test methodologies are not precise and/or foolproof. For example, software fault simulation techniques may be used to try to isolate a failing latch in a LSSD scan chain. However, such techniques consume processing time and may not be used when all LSSD scan chains included in the circuit design are broken (e.g., faulty). Further, software fault simulation techniques may often point to a set of possible faulty candidates (e.g., more than one latch included in the LSSD scan chain) rather than a single faulty latch.
Another method of testing and diagnosing (e.g., isolating a defect in) defective LSSD scan chains in a circuit design may include a noise injection or insertion technique. The noise injection or insertion technique involves partially powering-down, then powering-up the circuit design and scanning out data hoping that the latch after the fault in the circuit design will include the opposite value of the fault. However latches are usually asymmetrical, and therefore, tend to receive the same logic state after a power-down and subsequent power-up. Alternatively, external latch disturb techniques (e.g., using a laser, etc.) may be employed to test and diagnose LSSD scan chains. However, these external techniques are more suitable for Physical Failure Analysis (PFA).
Another method of testing and diagnosing (e.g., isolating a defect in) defective LSSD scan chains in a circuit design may include a lateral insertion technique, in which the broadside (e.g., data) port of one or more latches included in a LSSD scan chain are used to input (e.g., load) data to the one or more latches. Thereafter, the values may be unloaded for diagnosing the faulty LSSD scan chain. However, such a method requires excessive test generation. For example, data may be inputted to one or more latches included in the faulty LSSD scan chain via the broadside port of the one or more latches, and thereafter, scanned out of the LSSD scan chain until a faulty latch is found. The lateral insertion technique is not always feasible or successful.
By improving the diagnostic time for isolating a failing latch in a LSSD scan chain of the circuit design, improvements may be made quickly to the manufacturing yield of the circuit design, thereby ensuring successful and timely production of the circuit design. Therefore methods and apparatus for testing and diagnosing (e.g., isolating a defect in) a LSSD scan chain are desired.